Logic Synthesis and Optimization Based on Dual Logic

With the deficiency of the traditional Boolean logic in the logic functions minimization,an algorithm for the logic functions minimization by using both Boolean logic and Reed-Muller(RM) logic is proposed.By converting the product terms of a function into the disjointed products,and using the bit-wise operation of the disjointed products,the logic function's cover is divided into two parts which are suitable for RM logic implementation and Boolean logic implementation,respectively.Then the function is minimized with both RM logic and Boolean logic(dual logic) at the same time.Further,a method of the functional verification for dual logic is also proposed by checking whether the covers of two functions are equal or not.The proposed algorithm has been implemented in C and tested on MCNC benchmarks.The experimental results show that for the most test cases the proposed dual logic minimization algorithm produces fewer product terms in contrast to the method which only employs Boolean logic.