ETG (Easy Test Generation) Circuits

Rapid advances in IC technology are causing difficulties with testing of IC chips.Design For Testability(DFT)techniques have been proposed. Major disad vantages of these techniques are the degradation of circuit performance and the req uirement of a long and contiauous test mode. This paper presents a concept of an ETG (Easy Test Generation) circuit. An ETG circuit is one for which a complete test set (covering all modeled faults) can be generated with linear computational complexity in the circuit size.This paper first explains the difference between ETG and other DFT techniques,and then briefly describes ETG combinational circuits and ETG sequential circuits, and especially discusses ETG PLAs (Programmable Logic Arrays) in detail.An algorithm to modify a given PLA into an ETG PLA is prese nted, and some experimental results are given.As an example of ETG circuits,ETG PLAs show the feasibility of the ETG techniques.