Aging-aware Soft Error Rate Analysis for Nano-scaled CMOS Circuits

Technology scaling results in that the sensitivity of combinational circuits to soft errors and negative bias temperature instability（NBTI） effect to circuits is becoming more and more serious. In order to accurately compute single event transient（SET） induced soft error rate for combinational circuits in their life time, an aging-aware soft error rate analysis technique for nano-scaled CMOS circuits is proposed. Firstly, fault injection was simulated by means of reversing the output value of a gate cell, and then the related sensitized paths were retrieved by the proposed re-convergence aware sensitized path searching algorithm. Further, width of SET pulses generated in a gate cell was broadened by first-hit SET pulse broadening model, after mapping the PMOS threshold voltages calculated by NBTI models into PTM model cards, broadening ratio of pulses propagating through logic gate cells was measured by aging-aware HSPICE tool. As a result, SER induced by the broadened pulses latched by storage elements was accurately computed. Experimental results show that, the proposed technique improves 15% soft error rate accuracy on average in comparison with the aging-not-aware approach when the target circuits endure 10-years NBTI effect.