Co-design Environment Supporting Platform-Based System-on-Chip Design Methodology

We developed a hardware?software co-design environment named YH-PBDE for platform-based System-on-Chip (SoC) design method. After introducing the overall structure of YH-PBDE, we describe the three design levels and two mapping processes in YH-PBDE. Besides, we explain some key techniques used, including system modeling method using Constrained Taskflow Graph (CTG), hardware?software partitioning based on ant algorithm with initial pheromone, and performance constraint assignment method based on Hierarchical Directed Acyclic Graph (HDAG). We show the working flow of YH-PBDE with a case study on the system level design of recording-enabled MP3 player SoC chip, and the experimental results indicate the effectiveness of this hardware?software co-design environment.