A Timing-Aware 3D IC Bonding Optimization Method

Under impacting of process variation, the yield of the 3D IC mostly depends on the bonding strategies.In order to reduce the yield loss due to unmerited bonding orders, this paper proposes a bonding optimization method based on critical path delay to improve the yield in 3D chips bonding process.Path delay measurement is employed to obtain the timing characteristics of the pre-bond chips;and the chip with long paths is bonded to the one with short paths in different layers, which means use good one to save bad one.Two matching algorithms called grading and toothing are presented by formalizing the max yield problem with bipartite graph maximum matching model.Experimental results show that the proposed bonding method achieved much higher yield compared to random bonding.