Optimization of Static Power for Dual Threshold CMOS Circuits

When scaling down into deep sub-micron of VLSI design,the static power of ICs can’t be neglected.An algorithm to optimize the static power based-on dual-Vt is presented,which allows transistors with two different threshold voltages on the same chip. Experiments with the ISCAS85&89 benchmark circuits show above 20% static power can be cut down without violating the delay constraint （above 90% for large scale circuits）,the glitches/hazards of circuits can be greatly reduced,and the performance of the circuit can be improved.The project is sponsored by the 863 National High Technology R&D funds.