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Jia Yanming, Cai Yici, Hong Xianlong. Timing Driven Layer Assignment Considering Via Resistance and Coupling CapacitanceJ. Journal of Computer-Aided Design & Computer Graphics, 2009, 21(2): 196-202.
Citation: Jia Yanming, Cai Yici, Hong Xianlong. Timing Driven Layer Assignment Considering Via Resistance and Coupling CapacitanceJ. Journal of Computer-Aided Design & Computer Graphics, 2009, 21(2): 196-202.

Timing Driven Layer Assignment Considering Via Resistance and Coupling Capacitance

  • Aiming at optimizing interconnect timing directly,assigning proper routing layer resource and considering via-induced-delay and coupling-induced-delay simultaneously,a timing driven layer assignment algorithm for multilayer routing problem is proposed.This algorithm includes three phases: first,path based timing analysis is applied to find the timing-critical part of a circuit.Then a via aware timing model and a probabilistic coupling capacitance model are used to calculate the cost of assigning a net to a routing layer.Finally a greedy algorithm is used to perform layer assignment.Experimental results show that,it is necessary to optimize timing directly instead of merely controlling the amount of vias and couplings.
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