Data Prefetching Based Last-Level Cache Optimization for Chip Multiprocessors

The performance of last-level cache(LLC) has become a key factor affecting the overall performance of chip multiprocessors(CMP).Based on the LLC miss behaviorsimilarity among different nodes of the CMP system that processes parallel workloads,a data prefetching mechanism is proposed to significantly reduce the LLC miss rate.This paper starts from tracing the LLC miss behaviors,which is then utilized to identify the inter-core load miss correlation.In case of an load miss,if it is predicted to be followed by any further successive load misses of other nodes,the data block is simulteanously forwarded to the potential missing nodes.Experimental results demonstrate that,the proposed mechanism reduces the LLC miss rate by 9.8% and 18.4%,while improves the overall performance by 4.0% and 12.4% when considering 4-core and 16-core CMP systems.