An Improved Sequential Logic Optimization Algorithm Based on Invariant Generation and Induction

To optimize the circuit area and critical path delay simultaneously and fast in sequential synthesis,this paper presents an improved sequential logic optimization algorithm based on an "assume-then-prove" principle.Prior to applying bit-wise parallel simulation to derive initial candidate invariants,the algorithm makes use of registers sharing to reduce the number of the initial candidate invariants,with which the number of times in calling the SAT procedure can be decreased.Then,it merges the processes of base case and induction steps to improve the induction utilizing speculative reduction model.Therefore it can effectively reduce both the area and critical path delay of the implementation circuits,and improve the computational speed.Experiment results show that the presented algorithm achieves an average reduction in number of the registers and the number of the logic nodes by 41% and 48% respectively,and the critical path delay can be reduced by 30% on average.In comparison with similar method,the average runtime of the new algorithm decreased 17%.