A Reconfigurable Sub-Pixel Interpolation Architecture Design for Multi-standard Video Decoding

Subpixel interpolation is one of the most computation-intensive parts in various HD video decoding processes.The existing subpixel interpolation architectures have difficulties in achieving high performance and flexibility simultaneously.This paper presents a reconfigurable sub-pixel interpolation architecture for multi-standard video decoding.Based on the analysis and comparison of commonalities and differences among interpolation algorithms of various standards, a novel reconfigurable parallel-serial-mixed filtering architecture is proposed, which allows dynamical configuration of the data transfer path, the I/O data pattern and the filter computation unit.It supports various video coding standards including VC-1, H.264/263, AVS and MPEG-1/2/4.The experimental results show that this design can achieve the real-time multi-standard HDTV 1080p (1920x1088@30 fps) video decoding.Compared to previous work, the proposed design can support more types of HD video coding standards while consuming the same amount of silicon resources.It has been applied in a multimedia SoC chip.