Automatic Generation of Application Specific Instruction-Set Processors Directed by Transport Triggered Architecture

A method that can automatically generate application specific instruction-set processors （ASIP） is presented.This method is directed by transport triggered architecture （TTA） and can solve instructionset generation,retargetable compiler and micro-architecture design efficiently.TTA has only one type of instruction,i.e. MOVE,this avoid the instruction set generation problem；in the tool chain,the syntax translation and scheduling are independent,the scheduler don’t care about the syntax of function units,so the compiler is retargetable；micro-architectures are based on the same template,the register transfer level description of ASIP can be automatically generated.In addition,the performance optimization and connection optimization are both performed automatically.Applying this method to cipher algorithms validates its efficiency.