An Manhattan Cut-Line Generation Algorithm for the Topology of Clock Routing

Nowadays the IC industry has entered a era of large scale and high frequency, so the zero-skew and signal integrity in the clock routing become important problems to be resolved. Based on the Planar-DME topology generation algorithm, we present a Manhattan cut-line generation algorithm, which complete the conversion from the topology lines on the Euclidean plane to cut-lines on Manhattan plane and then construct the virtual channel for latter wire adaptation and connection. Applied to a pipelined clock tree building algorithm, finally we build a zero-skew planar clock tree. A prototype ClockStar is developed using the algorithm. Some examples have been tested and the results are promising.