Combinational Equivalence Checking Based on Circuit Topology Analysis

With the increasing of VLSI circuit size,using multiple verification engines has been an important methodology of formal equivalence checking for combinational circuits.A combinational equivalence checking method based on circuit topology analysis is presented.This method can correlate the circuit topology to the complexity of verification algorithm,thus decide the optimal verification engine beforehand and improve the efficiency of equivalence checking.The experimental results on ISCAS'85 benchmark circuits show the efficiency and the feasibility of the proposed method.