2D Analytical Model for On-Chip Interconnect Capacitance Extraction Based on Conformal Mapping Method

Based on the conformal mapping method, we rigorously derive analytical expressions for useful elementary capacitances, including the contributions of superposition electric fields, upon which an accurate 2D analytical model of interconnect capacitance is established within certain parameter ranges of cross section geometries of interconnect lines. It is verified through simulation that the mean square errors of analytical models for double-line system and multi-line system are less than 2% and 7% respectively. The proposed expressions excel other referenced expressions in capacitance extraction accuracy, being able to act as a competitive capacitance extraction method embedded in interconnect analysis and design tools.