Fast Heterogeneous IP Integration for SOPC Design

A system on a programmable chip （SOPC） design tool called ESIGE is presented.It provides an open structure that encapsulates heterogeneous soft IP cores from different providers,and hides the complexity of IP cores from the SOPC designers.IP cores with different implementation techniques and different bus interfaces can be integrated together.ESIGE integrates IP cores in a hierarchical and flexible way, supports complex integration structure.With virtual design and automatic IP integration,ESIGE reduces the complexity of SOPC design significantly.