Code Transformation-Based High-Level Synthesis Optimization Method for Zynq-SoC

To improve the performance of the SoC based on FPGA designs and reduce the time to market, this paper pro-poses an optimization approach for high-level synthesis based on the transformation of the high-level codes. Firstly, hardware and software partition of the high-level algorithm is explored to determine which part will be executed on the FPGA. Secondly, in allusion to hardware partition, approaches are applied to remove the data dependency between different functions, improve the parallelism of the loops and pipeline the loop body. Finally, the proposed method is applied to the Alpha-beta searching algorithm, which is used for designing Blokus-Duo game player. The experimental results show that the high-level codes can be transformed automatically to the appropriate pattern which is fit for the high-level synthesis to improve the performance. In comparison with the hardware implementation without code transformation, the proposed optimization method improves the running speed by 14 times.