EXTRACTION OF 2D CAPACITANCE FOR VLSI LAYOUT BASED ON BOUNDARY ELEMENT METHOD

This paper presents a two dimensional (2D) extraction of VLSI capacitance based on the boundary element method. By solving 2D Laplace equation, various kinds of capacitance including parasitic capacitance are obtained. Compared with other numerical methods, the extractor can not only prepare the input data easily, but also has high efficiency and precision. Through applying the extractor to several examples of VLSI layout, the calculated results show good coincidence with the experimental data.