Using the Whole Path Graphs (WPGs) Method for Generating Tests of CMOS Switch Level

An application of the WPGs Method in generating tests for CMOS switch level is described in this paper. Permanent line breaks and shorts are used to represent faults in a circuit. A line break fault is a fault which breaks a logic line so that conduction through the line is no longer possible. A line short fault is a fault which shorts the two terminals of a logic line so that the line is always conducting. The fault model is an extension of stuck-open (on), s.a.o (1), and can represent most of the possible failures observed in field practice. Cluster Shaped Logic Path Graphs (CLPGs) are analogous to connection grahps in4. One point to note is that CLPGs are subgraphs of CLuster WPGs, therefore we can use the concept of WPGs to detect multiple faults.