Low Power Parallel VLSI Architecture for LTE Turbo Decoder

Targeted to 3GPP LET standard,this paper proposes a parallell-structured turbo decoder in low power consumption based on the maximum a-posteriori algorithm.Taking advantage of the mathmetical property of the quadratic permutation polynomial,the address of each interleaver,in the parallel processing structure,is separated into two parts,block address and offset address in that block.An recursive algorithm is developed to calculate these two addresses in a parallel decoder,which leads to the parallelism can be any value,breaking the limitation of the power of 2.Relying on the developed algorithm a recursive VLSI architecture is presented,which significantly simplifies the extrinsic information interconnecting networks and avoids the usage of interleaver storage memory in the conventional approach,and remarkably decreass the power and area.Architecture level optimization strategies are also explored to further reduce the VLSI area and power consumption.Implemented with 40 nm technology,1.18V power supply and 283 MHz clock,post-layout shows that the decoder achieves 130 Mb/s throughout at 107 mW power consumption and 0.107 nJ/bit/iteration in energy efficiency.