Feasibility of Omitting the Step of State Reduction in Control Flow Synthesis

To solve the problem that control flow synthesis takes so much time that circuit design cycle is prolonged,this article analyzes the basic steps and problem of control flow synthesis,focusing on the special circumstance of finite-state machine that is handled by control flow synthesis,and discusses the feasibility of omitting the step of state reduction to save time.This article also puts forward a concrete scheme to omit the step of state reduction in EDA synthesis tool.