A Selective Dual Modular Redundancy Approach for FPGA Hardening Technique

Aiming at the excessive hardware overhead of existing FPGA hardening techniques, this paper proposes a selective dual modular redundancy scheme by utilizing the fault masking properties of logic gates to tolerate faults in FPGAs. Firstly, look up table(LUT) structure circuit model is established for each circuit, and fault sensitivity of each LUT in given circuit is calculated level by level according to fault propagation probability. Secondly, LUTs with higher fault sensitivity are duplicated, and an AND or OR logic is added to the duplicated LUT output as a voter so that certain faults are masked. Finally, fault injection experiments are carried on the hardened circuits to verify the proposed hardening technique. The experimental results on MCNC test set circuits show that, under the condition of the same overhead, the proposed approach can reduce more faults compared with existing methods. At the full redundant mode, the proposed approach can reduce faults by 84.3% on average, and for large circuits like apex2 and spla can reduce more than 97%.