Observability-Oriented Selective Triple Modular Redundancy for SRAM FPGA

This paper proposed an efficient scheme of observability-oriented selective triple modular redundancy（OSTMR） for SEU mitigation in SRAM-based FPGAs. The new technique operated on a lookup-table（LUT） network obtained after the technology mapping stage. A new notion of LUT observability was defined and theoretically calculated using signal probabilities of the nets on a given circuit. Then the entire set of LUTs was evaluated on the basis of signal probability and observability of LUTs. LUTs with higher observability were called SEU-sensitive LUTs and selected. Then the circuit was hardened against SEUs by applying triple modular redundancy to those SEU-sensitive LUTs. The experimental results on MCNC’91 benchmarks show that, with a small loss of reliability, the proposed OSTMR method could greatly reduce the area overhead of the hardened circuit compared with the common triple modular redundancy（TMR）. OSTMR triplicates only 37% LUTs on average comparing to full TMR with 200%. Even with such a low area requirement, the circuits produced by the OSTMR technique are observed to achieve a very high SEU immunity by 92.6%.