The Design and Implementation for a Software-Hardware Cooperative Loop Optimization Mechanism

In order to increase loop performance and reduce loop overhead, a software-hardware cooperative loop optimization mechanism suitable for multi-issue digital signal processor (DSP) is proposed in this paper.In this mechanism, based on the quantitative analysis of the loop body, the compiler inserts marking instruction in front of the effective loop body and deletes loop overhead instructions.A loop-overhead-reducing hardware unit is added to manage the loop counter and calculate the address of the instruction to be fetched according to the parameters from loop marking instruction.By employing this mechanism, loop overhead is avoided.The experimental results on the multi-issue DSP SuperV_EF01 show that, this mechanism can decrease the instruction cycles and assembly code size by 20.94%and 4.06%separately.