Technology Mapping Algorithm for FPGA with MUX-LUT Mixed Architecture

A technology mapping algorithm for doing area-optimal technology mapping for FPGA based on MUX-LUT mixed logic cell structure is presented. The algorithm composes mainly of a conversion from circuit of logic gates to MUX networks and a mapping from MUX networks to logic cells. The algorithm uses pattern-matching method to remove redundant MUX in order to reduce the area cost of the mapping result. We compared our algorithm with that used in XilinxTM FoundationTM system by a set of benchmark circuits. The comparison result is also presented.