Hierarchical Communication Model for Interface Synthesis in System-on-Chip Design

Based on the hardware software co-design platform environment (YH-PBDE) designed and developed by ourselves, this paper presents a stepwise-refined hierarchical communication model named HCM. This model follows the design tenet that computation and communication should be separated and it consists of three levels: systematic, virtual component and real component. The interface among the three levels is implemented by two methods: mapping and refining. Based on HCM, this paper expatiates on a novel algorithm flow of virtual-real component interface synthesis, providing a useful solution for the smooth communications between various intellectual property (IP) cores. The proposed model and approach can achieve an automatic integration between different IPs effectively, making reuse techniques possible.