A Temperature-Aware FPGA Placement Based on Vertical Diffusion

In this paper we propose an FPGA placement algorithm for temperature optimization based on vertical diffusion. It aims at reducing the effect of the increase in thermal gradient of FPGA on chip performance and reliability. Firstly, we analyzed the relationship between chip size and the temperature and thermal gradient of the chip through experiments. Secondly, according to the placed net list, we computed the hotspot region. Its boundary together with a diffusion coefficient was used to construct the proposed placement algorithm. In addition, we provided an adjustment mechanism of local positions to remove overlaps between logic blocks. Experimental results show a 7.5% and 20.3% reduction on average in peak temperature and thermal gradient respectively with a 3.4% and 1.4% increase in wire length and delay, in comparison with their counterparts in conventional placement algorithm.