Validation Analysis and Test Flow Optimization of VLSI Chip

Some validation analysis is conducted on a high-performance general-purpose processor. The defect detection capacity of different test items is listed and some conclusions are obtained. Based on the data of validation analysis, a heuristic algorithm is presented to optimize the test flow in saving the test time. The complexity of the proposed algorithm can be reduced from O(dn2ⁿ) to O(dn³) in comparison with the dynamic programming algorithm. Experimental results show the high efficiency of the proposed algorithm.