Synchronous Mechanisms Based Zero-Latency GRLS Communication Scheme

Globally asynchronous locally synchronous（GALS） combined with frequency scaling has become a popular and effective technique in chip power reduction.However,frequency switching penalty and crossing-domain communication may be harmful to the performance of design.This paper introduces a counter-based frequency scaling method,in which the new clock edges are generated according to the results of the counter.Based on this method a globally ratiochronous locally synchronous（GRLS） scheme is proposed.GRLS is targeting at communication between two clock domains whose frequencies are ratio-related.By use of the relationship on frequency and phase,synchronous mechanisms are employed to maintain the correctness and robustness of the scheme.GRLS achieves a zero-latency crossing-domain communication.Frequency switching can be finished in a cycle and the power and area penalties can be neglected.Experimental results of a memory system built with GRLS demonstrated its efficiency,and GRLS has been successfully applied in a commercial SoC.