Power Optimization Technique Based on Dual-logic Diagram Expression at Gate Level

To cope with the limitation of traditional Boolean logic based power optimization at logic level, power optimization method of logic function based on traditional Boolean(TB) logic and Reed-Muller(RM) logic called dual logic is proposed with gate level diagram expression. First, logic function is represented in TB logic and RM logic. Then gate level expression is obtained through iterative algebraic and Boolean decomposition. Further, gate-level power optimization is carried out under the guidance of the power cost. Finally, a two level power optimization method at variable level and gate level is implemented. Experimental results show that the proposed method is more efficient than the state-of-art academic and commercial synthesis tools.