Virtual SoC Platform Based Orthogonal Stimulus Verification Methodology for IP Designs

In the traditional IP verification methodology, module-level verification platform and stimulus generation flow have problems in low efficiency and poor reusability. To resolve these problems, an orthogonal stimulus verification methodology based on a virtual SoC platform is proposed. The virtual SoC platform is composed of system-component function models and external-device behavior models, which are described by high-level abstraction modeling method. Based on the platform, an orthogonal classification method is adopted. It divided communication from computation and optimized two different stimulus generation flows, one is for IP communication interface verification and the other is for IP internal logic verification. The experimental results of several IPs show that the proposed methodology can remarkably improve IP verification efficiency and enhance IP verification reusability while reducing verification complexity.