A Novel STACK Generation Technique for MOS Analog Cell Circuit Layout

This paper proposes a new technique to automatically generateSTACK layout for MOS analog cell circuits. The circuit net-list is first mapped into a diffusion graph. Based on the diffusion graph, circuit partition, pattern recognition and symmetry searching are carried out to generate sub-graphs, each of which can be implemented by a STACK. The proposed symmetry searching algorithm can find the maximal symmetry structures in a none fully symmetric circuit. To guarantee the generation of a Eularian trail, the Atallah Eularian trail generation algorithm is improved by employing the dummy adding technique. In order to evaluate the performance of a generated STACK, a distributed parasitic capacitance model is applied to calculate the STACK node parasitic capacitance, as well as the calculation of STACK area and shape.