PERFORMANCE-DRIVEN TECHNOLOGY MAPPING FOR LOOKUP-TABLE TYPE FPGAs

This paper presents a performance driven technology mapping algorithm for LUT type FPGAs．The algorithm fully exploits the characteristics of the nodes during the mapping phase and calculates the parameters of the nodes．Linear Programming is used to give out the objective function and the correspondent constraints of the network．The problem of the network is converted to a pure mathematics problem —— programming problem to solve while mapping problem is to allocate the attributes over all the nodes to meet the objective function and constraints．Better results of area and delay have been achieved compared to other algorithms．