A Simulated Annealing FPGA Placement Algorithm Based on Unified Critical Path Delay

In traditional simulated annealing FPGA placement algorithm,the timing quality of one layout is measured by timing cost which is calculated based on its critical path delay(CPD).In some circumstances,the timing cost and the layout transformation does not match.In the proposed algorithm,the unified CPD datum is set,the probability of accepting a move which exceeding CPD is reduced by introducing punishment coefficient,and the setting standards of datum value is made according to influence of punishment coefficient on CPD convergence,thus the timing cost calculated based on unified CPD can match layout transformation.Experimental results are given to show the efficiency of our proposed algorithm.