On Chip Run-Time Power-Estimate Analyze and Design

For the purpose of providing the run-time power information to the operating system, and facilitating fast and accurate power management, we propose a run-time power-estimate system which is based on clock gating cells monitoring.This system records the processor's clock gating toggle information, and then acquires the hot-spots of the chip, finally, provides the necessary run-time power information to the operating system according to the result which is computed by hardware using a power model.The power model is established through the pre-silicon netlist simulation.This design is hardware integrated, and structure unrelated.It has the advantage of high speed, small overhead, low reduction of processor performance and high accurate.Experimental results on FPGA platform show that this system is faster than traditional simulation by nearly 40 times, and has a small deviation in 5% compared with the result of EDA tools.