Congestion Driven Placement for Three Dimensional Integration Chip Design Using Uniformity Modeling Approach

The recent popularity of three dimensional(3D) IC technology stems from its enhanced performance capabilities and reduced wiring length.To improve the routability and performance of 3D IC design,we develop placement algorithm to reduce congestions of 3D circuit design.Our algorithm consists of three phases.Firstly,in global placement phase,we use quadratic uniformity modeling approach to integrate congestion,cell distribution and wirelength optimization into one quadratic function,and utilize quadratic programming to solve the function to get the position of cells in 3D space.Secondly,we propose congestion aware layer assignment algorithm to assign the cell into different layers.Finally,detailed placement is employed to remove overlaps,optimize wirelength and reduce congestion in each layer.Experimental results show that our algorithm is efficient with 15% congestion reduction and only 3% wirelength increase.