Liu Qin, Wei Daozheng. The Research and Implementation of Parallel Fault Simulation for Digital CircuitsJ. Journal of Computer-Aided Design & Computer Graphics, 1992, 4(2): 8-13.
Citation:
Liu Qin, Wei Daozheng. The Research and Implementation of Parallel Fault Simulation for Digital CircuitsJ. Journal of Computer-Aided Design & Computer Graphics, 1992, 4(2): 8-13.
Liu Qin, Wei Daozheng. The Research and Implementation of Parallel Fault Simulation for Digital CircuitsJ. Journal of Computer-Aided Design & Computer Graphics, 1992, 4(2): 8-13.
Citation:
Liu Qin, Wei Daozheng. The Research and Implementation of Parallel Fault Simulation for Digital CircuitsJ. Journal of Computer-Aided Design & Computer Graphics, 1992, 4(2): 8-13.
The Research and Implementation of Parallel Fault Simulation for Digital Circuits
This paper implements a fault simulation system for digital circuits. The concept of sensitizing -in put is used to enhance the efficiency of combinational circuits. For sequential circuits, we expand the flip-flops to basic gates. As a result.the esperimental results of 10 ISCAS Benchmark Circuits are given.
DownLoad: