CHEN Dong-Ying, LIU Ming-Ye. Research on Acceleration of VHDL Simulator byJ. Journal of Computer-Aided Design & Computer Graphics, 2001, 13(7): 586-589.
Citation:
CHEN Dong-Ying, LIU Ming-Ye. Research on Acceleration of VHDL Simulator byJ. Journal of Computer-Aided Design & Computer Graphics, 2001, 13(7): 586-589.
CHEN Dong-Ying, LIU Ming-Ye. Research on Acceleration of VHDL Simulator byJ. Journal of Computer-Aided Design & Computer Graphics, 2001, 13(7): 586-589.
Citation:
CHEN Dong-Ying, LIU Ming-Ye. Research on Acceleration of VHDL Simulator byJ. Journal of Computer-Aided Design & Computer Graphics, 2001, 13(7): 586-589.
Measures to accelerate the simulation of large scale IC design，based on an actual high level auto-synthesis system are explored．After analyzing and comparing various kinds of simulation algorithms as well as investigating the existing simulation form and algorithm，we fi-nally embed the system-cell library （IDEA） into simulator’s core and accelerate the speed of VHDL simulator by 2to 4times．
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