Test Pattern Merging Algorithms for Sequential Circuits

The test sequence for sequential circuits usually consists of test patterns for each single fault.Two test pattern merging algorithms are presented to reduce the depth of total test sequence and thus reduce test time and power consumption.Through the concept of merging flexibility, the proposed algorithms sort the test patterns respectively, and then progressively merge the test patterns so as to construct the total test sequence for concerned circuit.Compared to previous Greedy-based algorithm, the proposed ones can obtain better results with the same computing complexity.Experimental results on ISCAS89 benchmark circuits show that the average performance increases by 4.96% and 8.23% respectively.The corresponding fault simulation results show that the fault coverage is a little improved and the resolution varies slightly.