A General DFD Infrastructure for Chip Multiprocessor

Post-silicon debugging is becoming more and more important in modern integrated circuit design.Hence,design for debug(DFD) is proposed to facilitate post-silicon debugging.The DFD in multi-core processors are very complicate,as there are lots of different components contained in a multi-core processor,and each of them have its own debugging requirements.In this paper,we propose a general DFD infrastructure for chip multiprocessor(CMP) that contains several simple monitors to watch and control the network on chip(NoC).All monitors are connected to a centralized controller,which gathers information and communicates with debugging host using EJTAG port.Compared with traditional DFD infrastructures,the proposed infrastructure is modularized,low cost,and general.This DFD infrastructure has been adopted by a state-of-art industry CMP Godson-3B.Experimental results demonstrated that the DFD infrastructure can work under high frequency and high data bandwidth environments.