VHDL Arithmetic Operator Synthesis in RTL Synthesis

As the behavior of digital system can be fully described by the register transfer level （RTL）behavior descriptor，so RTL synthesis has become the mainstream design method in EDA domain．Arithmetic operator is a kind of operators which is very difficult to synthesize in RTL synthesis．In this paper，we analyze all restrictions on arithmetic operators set by IEEE，and set forward our viewpoint on some arithmetic operators．In addition，we give forth implement solutions for each arithmetic operator and underline those solutions which suit RTL synthesis．Fi-nally，the paper presents tests done on the RTL synthesis tool developed by the authors，which show that these implement solutions are feasible and effective．