Distributed Vernier Based Interconnect Testing in 2.5D IC

To cope with several problems in the existing 2.5 D IC interconnect test methods, such as poor applicability, high area overhead and resolution instability. This paper proposes a technique for interconnect testing based on distributed vernier method. First of all, two kinds of vernier structures, including regular vernier and ring veriner designs, were selected according to the number and distribution of the interconnect. Then, all the delay cells of the vernier delay line are evenly distributed to each interconnect, so that all interconnects share the same vernier delay line. Finally, the interconnect delay was quantized into digital code. In this paper, the test time and area overhead are both considered, which can meet the requirements of complex integrated circuits design. The experimental results show that, the area overhead of the two distributed veriner methods are decreased by 52.6% and 23.7% respectively, compared with the existing methods. When the distance between adjacent interconnects changes, the stability of the measurement resolution is improved by 70%.