Failure Probability Estimation for Digital Circuits Considering Single Event Multiple Transients

To accurately compute the failure probability of digital circuits, a failure probability estimation method considering SEMT is proposed. This approach extracted SEMT fault position pairs by parsing circuit netlist. By using a double exponential current source model, fault injection was simulated on a particle stroked gate. Further, SEMT pulses in a fault position pair were converted to an overlapped SET pulse by means of SEMT pulse composite model. By propagating the overlapped SET pulse to downstream gate cells along the data paths, logical masking, electrical masking and timing masking were jointly evaluated with the proposed SEMT pulse masking model. As a result, the overall circuit failure probability was precisely calculated by the proposed failure probability estimation technique. Experimental results show that the proposed technique is more accurate comparing with the similar method and the relative difference is only 2% comparing with Monte Carlo method, thus the proposed method is valuable to fault tolerance design of ICs for selective hardening.