A Simulation-Based Verification Method for SoC Bus System

We propose a simulation-based method in the verification of SoC bus system. By the method, constrained-random vector is used to make simulation first; then a coverage analysis is made in the simulation process until a certain coverage statistics is obtained. Finally, the test vector is manually generated. We use this method to verify a SoC system and get a satisfactory result by reducing the time of simulation effectively.