Implementation of Specification and Verification Environment for Embedded System

Design environment is introduced to specify and verify the functionality and performance of embedded system. First, the state charts diagram of Unified Modeling Language (UML) is used to specify the states of a system in a full active period, and the active diagram is used to depict the functions of every process in one state, the constraint conditions of system are also expressed by Object Constraint Language. Second, in order to execute simulation and verification of a specified system, the UML2SC is developed to convert the system specification of UML into SystemC. Finally, an application example using the above approach is illustrated.