Delay Test Generation for Processors Combining RTL and Gate Level Netlist

An instruction-based path delay test generation method for the datapath of a processor is proposed,which apply the processor’s own instructions in normal operation mode to test itself.Dataflow-state matrix is extracted for each instruction,based on the matrix,paths are classified into functional untestable paths （FUPs） and potential functional testable paths （PFTPs）.The potential test instructions for PFTPs are stored and the control and data constraints are extracted.Constrained combinational non-robust delay test pattern generation is applied.The final test instructions are composed of controllability instruction（s）, potential test instruction（s） and observability instruction（s）. The instruction set architecture,register transfer level （RTL） description along with gate level netlist are used in the approach.Experimental results indicate that a significant percentage of functional untestable paths are recognized in early stage and the control and data constraints do a great deal to help generating the test vectors that can be mapped into test instructions for PFTPs.Experimental results also show that the proposed method takes a much shorter CPU time than the earlier work.