SoC Test Scheduling Model Based on ACSR

Pipelined test under constraint of power dissipation is preferable for minimal overall system test application time to keep the chip under test from being destroyed．Reasonable scheduling is imperative for optimal SoC test automation for optimal test resources allocation and test time minimization．A SoC test scheduling model based on algebra of communicating shared resources is proposed,and related theorems for transforming timed label transition system model of concurrent core testing into ACSR descriptions are given．The pipelined tests are mapped into concurrent processes．Test resources are modeled as ACSR resources,and priorities are used to avoid test conflicts to achieve maximum test parallelism under power dissipation．Experimental results indicate the advantage of our approach to SoC test scheduling for minimal test application time over the classical solutions．