Virtual Channel Routing Algorithm for GHz Zero-Skew Clock Tree Layout

With the progress of VLSI technology, high performance chips have been operating at multi-GHz frequency. The algorithms of either controlling the wire length or using the Elmore delay model for clock tree routing are no longer suitable for GHz circuits. A novel routing algorithm based on virtual channel generation is presented. Relying on pipe line scheme, it can be applied to planar routing for clock tree layout. The line segments in the constructed virtual channel are adjusted to avoid overlapping when global routing is finished. A prototype ClockStar is developed using the algorithm. Some examples have been tested and the results are promising.