Translation of VHDL Description to Petri Net in High Level Synthesis

This paper puts forward a Petri net generation algorithm based on execution paths. The algorithm extracts all functions and timing information from the VHDL description and generates Petri net as an intermediate representation identical to the VHDL description. A condition tree is used to store various conditions in a structured way. The executing conditions of all statements and transition conditions in Petri net are generated directly from the condition tree. The generated Petri net stores precisely the I/O timing information in VHDL description to guide the scheduling of I/O operation process. Based on Petri net, various I/O scheduling modes can be readily implemented.