THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPING

PENG Yu-Xing; CHEN Shu-Ming; CHEN Fu-Jie

PENG Yu-Xing, CHEN Shu-Ming, CHEN Fu-Jie. THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPINGJ. Journal of Computer-Aided Design & Computer Graphics, 1998, 10(4): 355-361.

Citation:

PENG Yu-Xing, CHEN Shu-Ming, CHEN Fu-Jie. THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPINGJ. Journal of Computer-Aided Design & Computer Graphics, 1998, 10(4): 355-361.

Citation:

PENG Yu-Xing, CHEN Shu-Ming, CHEN Fu-Jie. THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPINGJ. Journal of Computer-Aided Design & Computer Graphics, 1998, 10(4): 355-361.

THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPING

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This paper presents a performance-driven technology mapping algorithm. Firstly, it gives a technology mapping algorithm for delay minimization. And then, it gives a area optimization algorithm without increasing delay.

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THE TIMING/AREA OPTIMIZATION ALGORITHM FOR LUT BASED FPGA TECHNOLOGY MAPPING

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