An Approach of Power Optimization for De-synchronized Circuits

By considering the influence of operations and operands on the power of asynchronous pipelines, an improved de-synchronization flow is proposed to resolve the power redundancy problem in conventional de-synchronized circuits.First, an iterative multiplier is used to show the power redundancy problem in detail.Then, two different schemes are utilized to optimize the data path and control path respectively.The narrow-width operand characteristic is employed to optimize the data path, while operation behaviors are analyzed to optimize the control path.At last, the proposed flow is used to reduce the power consumption in an asynchronous TTA processor core.Experimental results show that the proposed method can achieve up to 40% power reduction for the de-synchronized TTA processor core.